1. Field of the Invention
The present invention relates to aligning or synchronizing multiple clock synthesizers or phase-locked loops (PLLs) that operate in parallel.
2. Discussion of the Related Art
Synchronization of timing signals is required, for instance, when aligning data sampling events in analog-to-digital converters that are driven by clock signals. Similarly, synchronization of timing signals is required to phase-align different carrier radio waves to achieve constructive interference. There are many systems that require—either because the number of clock signals they used or the spatial separations between the clocked devices therein—alignment of multiple clocking devices to a common time or phase.
Generally, a high frequency clocking signal may be synthesized from a lower frequency system reference signal (“reference signal fREF”) using a PLL. Often, using a PLL, a clock synthesizer creates a common high-frequency signal from reference signal fREF. The common high-frequency signal is then used to drive individual frequency dividers to produce multiple signals of different frequencies. Because of their digital nature, the signals from the frequency dividers may have random output phases. The PLL may also make use of digital frequency dividers that have random phase characteristics. The PLL can remove some, but not all, phase uncertainties. Clock synchronization is required to consistently force a single predetermined phase relationship among the frequency dividers.
FIG. 1 illustrates the operations of prior art PLL 100. In FIG. 1, PLL 100 uses feedback signal fVCO to align the phase of voltage controlled oscillator (VCO) 101 to the phase of incoming frequency reference signal fREF. As shown, feedback signal fVCO is output from VCO 101 to drives frequency divider 102, which has a frequency division ratio N. Frequency divider 102 is referred to as the “N-divider” or the “feedback divider”. Frequency reference signal fREF is provided to frequency divider 103, which has a frequency division ratio R. Frequency divider 103 is referred to as the “R-divider” or the “reference divider.” Phase detector 104 compares the output signals of the R-divider and the N-divider to adjust the frequency of VCO 101 so as to align the phases of the output signals of the R-divider and the N-divider. In steady state, feedback signal fvco and reference signal fREF are related by:
      f    VCO    =            f      REF        ⨯          N      R      In FIG. 1, signal fOUT represents an additional frequency division provided by output frequency divider 105, which reduces the frequency of signal fvco by a factor of M, M≧2:
      f    OUT    =            f      REF        ⨯          N              R        ⨯        M            The uncertainty of the starting state of frequency divider 103 (i.e., the R-divider) causes the phase of signal fVCO relative reference signal fREF to be indeterminate. An additional degree of phase uncertainty is in signal fOUT, due to output frequency divider 105.
The output signal of a digital frequency divider has one of K possible phases for a given frequency division ratio K. For K=1, there is no phase uncertainty, as there is only one phase possibility. Phase uncertainty occurs when K is greater than or equal to 2. Thus, to provide a deterministic phase relationship between fvco and fREF, the R-divider must have a known phase at a known time. FIG. 2 illustrates the two possible phases for fvco, as a result of phase uncertainty in the R-divider. As shown in FIG. 2, for frequency division ratios R=2 and N=5, fVCO=2.5×fREF. A similar phase uncertainty is present in signal fOUT with respect to fvco and fREF, where output frequency divider 105 has a frequency division ratio M≧2.
U.S. Pat. No. 8,819,472 teaches clock synchronization of multiple cascaded dividers in a series configuration (“series-connected clock synchronization system”), using a common synchronization signal. In the '472 patent, a “clock tree” of clock signals is created by connecting dividers in series, with each divider having an input signal and multiple output signals. Each cascaded divider adds timing uncertainty as a result of variations of clock propagation delay, and as a result of noise in the form of clock jitter. The resulting overall noise and clock uncertainty depend upon the number of dividers present between the reference signal and the output clock signal in question. The '472 patent teaches a method for creating a deterministic phase relationship. FIG. 3 shows a series-connected clock synchronization system according to teachings of the '472 patent.